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ICS5342 GENDAC 16-Bit Integrated Clock-LUT-DAC
General Description
The ICS5342 GENDAC is a combination of dual programmable clock generators, a 256 x 18-bit RAM, and a triple 8-bit video DAC. The GENDAC supports 8-bit pseudo color applications, as well as 15-bit, 16-bit, and 24-bit True Color bypass for high speed, direct access to the DACs. The RAM makes it possible to display 256 colors selected from a possible 262,144 colors. The dual clock generators use Phase Locked Loop (PLL) technology to provide programmable frequencies for use in the graphics subsystem. The video clock contains 8 frequencies, all of which are programmable by the user. The memory clock has two programmable frequency locations. The three 8-bit DACs on the ICS5342 are capable of driving singly or doubly-terminated 75 loads to nominal 0 - 0.7 volts at pixel rates up to 135 MHz. Differential and integral linearity errors are less than 1 LSB over full temperature and VDD ranges. Monotonicity is guaranteed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather than by modifying the color palette. ICS is the world leader in all aspects of frequency (clock) generation for graphics, using patented techniques to produce low jitter video timing.
Features
* * * Triple video DAC, dual clock generator, and 16 bit pixel port Dynamic mode switch allows switching of color depth on a pixel by pixel basis 24 (packed and sparse), 16, 15, or 8-bit pseudo color pixel mode supports True Color, Hi-Color, and VGA modes High speed 256 x 6 x 3 color palette (135 MHz) with bypass mode and 8-bit DACs Eight programmable video (pixel) clock frequencies (CLK0) DAC power down in blanking mode Anti-sparkle circuitry On-chip loop filters reduce external components Standard CPU interface Single external crystal (typically 14.318 MHz) Monitor sense Internal voltage reference 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions Very low clock jitter Two latched frequency select pins or three non-latched frequency select pins (programmable) Hardware video checksum for manufacturing tests
* * * * * * * * * * * * *
Block Schematic
PCLK COMPARE 24 P0-P15 BUFF. LATCH PIXEL ADR AND MASK D0-D7 WR* RD* RS0-RS2 STROBE CS0-CS2 BLANK* 16 MICROPROCESSOR INTERFACE 8 16 TIMING GEN.
CTL 8 PLL PARAMETER & CLK0 PLL BYPS
SENSE* RED GREEN BLUE RSET VREF
COLOR PALETTE 256 x 18 BIT
MUX 18
NORM
LATCH
24
TRIPLE 6/8-BIT DAC
MUX.
PCLK
2X MODE CLK0
XIN
XTAL OSC
XOUT
1 PLL PARAMETER & CLK1 PLL
CLK1 5342_01.ai
REV. 0.9.0
ICS5342 GENDAC
Pin Configuration Pin Configuration
CGND CLK1 P14 P15 D0 D1 D2 D3 D4 D5 D6 D7 WR* RS0 RS1 MSW CGND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CVDD CLK0 BLANK* STROBE* RD* P13 CS1 CS0 P12 SENSE* P11 P10 P9 P8 RS2 N/C CVDD 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
GENDAC II ICS5342
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
40 41 42 43
CGND PCLK P7 P6 P5 P4 P3 P2 P1 P0 XVDD XOUT XIN XGND VREF N/C DGND
CVDD N/C N/C N/C N/C N/C N/C N/C N/C AGND RED GRN N/C BLUE AVDD RSET DVDD
27 28 29 30 31 32 33 34 35 36 37 38 39
5342_02
ICS5342 (68-pin PLCC)
Pin Description (68-pin PLCC)
Symbol D7 - D0 Pin # 21-14 Type I/O Description Systems data bus bidirectional data I/O lines - used by host microprocessor for internal register read and write operations (using active low RD and WR respectively) for six internal registers: Pixel Address, Color Value, Pixel Mask, PLL Address, PLL Parameter, and Command During the write cycle, the rising edge of WR latches the data into the selected register (set by the status of the three RS pins). The rising edge of RD determines the end of the read cycle. The RD set logical high indicates that data I/O lines no longer contain information from the selected register and will be tri-stated. RAM/PLL read enable bus control signal - in active low state, any information present on the internal data bus is available on the Data I/O lines, D0-D7 Active low RAM/PLL write enable bus control signal - controls write timing on microprocessor interface inputs, D0-D7 Register address select 0 inputs - control selection of one of six internal registers - inputs are sampled on falling edge of active enable signal (RD or WR) Crystal input - connect to 14.318 MHz crystal Crystal output - connect to 14.318 MHz crystal Mode switch - digital control for selecting primary and secondary pixel color modes - low selects primary mode - connect to ground if not used
RD WR RS2-RS0 XIN XOUT MSW
5 22 63,24,23 48 49 25
Input Input Input Input Output Input
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ICS5342 GENDAC
Pin Description (68-pin PLCC)
Symbol CLK1 CLK0 CS0 CS1 VREF RSET SENSE* Pin # 11 8 2 3 46 42 68 Type Output Output Input Input I/O Input Output Description Memory clock output - used to time video memory Video clock output - provides a CMOS level pixel or dot clock frequency to graphics controller - output frequency is determined by values of PLL registers Clock select 0 - The status of CS0-1 determines which frequency is selected on the CLK0 (video) output. Clock select 1- status of CS0-1 determines which frequency is selected on CLK0 (video) output Internal reference voltage - normally connects to a 0.1f capacitor to ground - to use external Vref, connect 1.235V reference to this pin Resistor set - pin used to set current level in analog outputs - usually connected through 1/4W, 1% resistor to ground Monitor sense - Pin is active low when any of red, green, or blue outputs >385mV. Sense output is high when all analog outputs are < 275 mV. Chip has on-board comparators and internal 1.235 V voltage reference. This signal is used to detect monitor type. Color signals from DAC analog outputs - Each DAC comprises several current sources of which outputs are added together according to the applied binary value. The outputs are typically used to drive a CRT monitor. Pixel address lines - Byte-wide information is latched by the rising edge of PCLK when using the color palette, and is masked by the Pixel Mask register. Values are used to specify the RAM word address in default mode (accessing RAM). In HiColor XGA, and True Color modes, they represent color data for the DACs. Ground inputs if they are not used. Pixel Clock - rising edge of PCLK controls latching of the Pixel Address and BLANK* inputs - clock also controls progress of these values through the threestage pipeline of the Color Palette RAM, DAC, and outputs latches input clock select signals CS0-CS1 Composite BLANK* Signal, active low. When BLANK* is asserted, outputs of DACs are zero which blacks screen. DACs are automatically powered down to save current during blanking. Color palette may still be updated through D0-D7 during blanking. CLK1 Power Supply - connect to DVDD CLK0 power supply - connect to AVDD DAC power supply - Connect to AVDD Digital power supply Crystal oscillator power supply- connect to AVDD CLK power supply - connect to DVDD VSS for CLK1 - connect to ground. VSS for CLK0 - connect to ground VSS for crystal oscillator DAC ground - connect to ground Digital ground - connect to ground VSS for CLK - connect to ground Not connected - leave floating or tie to ground
BLUE GREEN RED P15- P0
40 38 37 13,12,4,1 , 67-64, 58-51 59
Output Output Output Input
PCLK
Input
STROBE* BLANK*
6 7
Input Input
CVDD CVDD AVDD DVDD XVDD CVDD CGND CGND XGND AGND DGND CGND N/C
9 27 41 43 50 61 10 26 47 36 44 60 28-35, 39,45, 62
-
3
ICS5342 GENDAC
Internal Registers
RS2 RS1 RS0 Register Name Description (all registers can be written to and read from) The GENDAC has a single pixel address register which can be accessed through either register address 0,0,0 or 0,1,1 - reading from either register gives the same result. Writing a value to address 0,0,0: - specifies an address within the color palette RAM - initializes the Color Value register Writing a value to address 0,1,1: - specifies an address within the color palette RAM - loads Color Value register with contents of location in addressed RAM palette and then: - increments Pixel Address register Writing to this 8-bit register is done before writing one or more color values to color palette RAM. Writing to this 8-bit register is done before reading one or more color values from color palette RAM. The 18-bit Color Value register acts as a buffer between the microprocessor interface and the color palette. A value may be read from or written to this register using a three-byte transfer sequence. The color value is contained in the least significant 6 bits, D0-D5, of the byte read - the most significant 2 bits are set to zero. The same 6 bits are used when writing a byte. When reading or writing, data is transferred in the same order - red byte first, then green, then blue. Each transfer between the Color Value register and the color palette replaces the normal pixel mapping operations of the GENDAC for a single pixel. After writing three definitions to this register, its contents are written to the location in the color palette RAM specified by the Pixel Address register, before that register increments. After reading three definitions from this register, the contents of the location in the color palette RAM specified by the Pixel Address registers are copied into the Color Value register, and the Pixel Address register increments. The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel Address value applied to the Pixel Address inputs (P7-P0). A one in a position in the mask register leaves the corresponding bit in the Pixel Address unaltered, while a zero sets that bit to zero. The Pixel Mask register does not affect the Pixel Address generated by the microprocessor interface when the palette RAM is being accessed. Writing to this 8-bit register is performed prior to writing one or more PLL programming values to the PLL Parameter register. Writing to this 8-bit register is performed prior to reading one or more PLL programming values from the PLL Parameter register.
0 0 0
1 1 0
1 1 1
Pixel Address WRITE Pixel Address READ Color Value
0
1
0
Pixel Mask
1 1
0 1
0 1
PLL Address WRITE PLL Address READ
4
ICS5342 GENDAC
Internal Registers
RS2 1 1 RS1 0 RS0 Register Name Command Description (all registers can be written to and read from) This 8-bit register selects color mode, for instance 8-bit Pseudo Color, Hi-Color, True Color, or XGA, and DAC power down. The registers are reset to pseudo color mode on power up. There are 16 PLL parameter registers accessible as indexed by Read/Write registers. Parameter registers 0F and 0D-00 are two bytes long and 0E is one byte long. Register 0E is a control register. The bits of this register include clock select and enable functions, the rest contain PLL frequency parameters. After writing the start index address in the PLL address register, these registers can be accessed in successive two (or one) bytes. The address register auto increments after one (0E) or two bytes to access the entire register
1
0
1
PLL Parameter
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ICS5342 GENDAC
Absolute Maximum Ratings
Power Supply Voltage........................................................7 V Voltage on any other pin.............. GND - 0.5V to VDD + 0.5V Temperature under bias ................................ - 40 C to 85 C Storage Temperature................................... - 65 C to 150 C DC Digital Output Current ......................................... 25 mA Analog Output Current ................................................45 mA Reference Current......................................................-15 mA Power Dissipation ......................................................... 1.0 W
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics DC CHARACTERISTICS (note: J)
Parameter Positive supply voltage Input logic "1" voltage Input logic "0" voltage Reference current Reference voltage Digital input current Off-state digital output current Average power supply current DACs in power down mode Sense logic "1" Sense logic "0" Clock logic "1" Clock logic "0" Logic "1" Logic "0" XIN input clock rise time XIN input clock fall time Frequency change of CLK0 and CLK1 over supply and temperature Symbol VDD VIH VIL IREF VREF IIN IOZ IDD IDACOFF VOHS VOLS VOHC VOLC VOH VOL XCLKr* XCLKf* FD Min. 4.75 2.0 - 0.5 -7.0 1.10 Max. 5.25 VDD+0.5 0.8 -10 1.35 10 50 250 50 2.4 0.4 2.4 0.4 2.4 0.4 15 15 0.05 Units V V V mA V A A mA mA V V V V V V ns ns % Test Conditions
VDD=max, VDDVINGND VDD = max, VDDVINGND IO = max, Digital outputs unloaded no palette access IO= -0.4mA IO = 0.4mA IO = -12.0mA IO = 12.0mA IO = -3.2mA, note K IO = 3.2mA, note K TTL levels TTL levels with respect to typical frequency
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ICS5342 GENDAC
DAC Characteristics
Parameter Maximum output voltage Maximum output current Full scale error DAC to DAC correlation Integral Linearity, 6-bit Integral Linearity, 8-bit Full scale settling time*, 6-bit Full scale settling time*, 8-bit Rise time (10% to 90%)* Glitch energy* Symbol Vo (max) Io (max) Min Max 1.5 21 5 2 0.5 1 28 20 6 200 Units V mA % % LSB LSB ns ns ns pV.s Test Conditions Io 10 mA Vo 1V note A, B note B note B note B note C note C note C note C
PLL AC Characteristics
Parameter Clock 0 operating range Clock 1 operating range Output clocks rise time* Output clocks fall time* Duty Cycle* Jitter, one sigma* Jitter, absolute* Input reference frequency* * Characterized values only Symbol f0 f1 tr tr dt j1s jabs fref Min 25 25 Max 135 135 3 3 60/40 130 ps 300 ps 25 Units MHz MHz ns ns % ps ps MHz Test Conditions
25 pF load, TTL levels 25 pF load, TTL levels
40/60 -300 ps 5
Typically 14.318 MHz
AC Electrical Characteristics (note: J)
Parameter PCLK period PCLK jitter PCLK width low PCLK width high Pixel word setup time Pixel word hold time BLANK* setup time BLANK* hold time PCLK to valid DAC output Symbol tCHCH tCHCH* tCLCH tCHCL tPVCH tCHPX tBVCH tCHBX tCHAV* 80 MHZ Min 12.5 5 5 3 3 3 3 20 Max 2.5 3.6 3.6 3 2 3 2 20 110MHz Min 9.09 Max +2.5 3 3 2 1 2 1 20 135Mhz Min 7.4 Max Units ns % ns ns ns ns ns ns ns Test Conditions note D
note E note E note E note E note F
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ICS5342 GENDAC
AC Electrical Characteristics (note: J)
Parameter Differential output delay WR* pulse width low RD* pulse width low Register select setup time Register select setup time Register select hold time Register select hold time WR* data setup time WR* data hold time Output turn-on delay RD* enable access time Output hold time Output turn-off delay Successive write interval WR* followed by read interval Successive read interval RD* followed by write interval WR* after color write RD* after color write RD* after color read WR* after color read RD* after read address write SENSE* output delay XIN input clock rise time Symbol tCHAV tWLWH tRLRH tSVWL tSVRL tWLSX tRLSX tDVWH tWHDX tRLQX tRLQV tRHQX tRHQZ tWHWL1 tWHRL1 tRHRL1 tRHWL1 tWHWL2 tWHRL2 tRHRL2 tRHWL2 tWHRL3 tSOD tXCLKR* 50 50 10 10 10 10 10 10 5 40 3 20 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 8 (tCHCH) 8 (tCHCH) 8 (tCHCH) 1 15 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 8 (tCHCH) 8 (tCHCH) 8 (tCHCH) 1 15 3 20 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 4 (tCHCH) 8 (tCHCH) 8 (tCHCH) 8 (tCHCH) 1 15 80 MHZ Min Max 2 50 50 10 10 10 10 10 10 5 40 3 20 110MHz Min Max 2 50 50 10 10 10 10 10 10 5 40 135Mhz Min Max 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle cycle cycle cycle cycle cycle cycle cycle s ns Test Conditions note G
write cycle read cycle write cycle read cycle
note H note I note I note I note I note I note I note I note I note I
TTL levels
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ICS5342 GENDAC
AC Electrical Characteristics (note: J)
Parameter XIN input clock fall time * Characterized values only Symbol tXCLKF* 80 MHZ Min Max 15 110MHz Min Max 15 135Mhz Min Max 15 Units ns Test Conditions TTL levels
Notes: A. Full scale error is derived from design equation: {[(F.S.IOUT)RL - 2.1(IREF)RL] / [2.1(IREF)RL]} 100% VBLACK LEVEL= 0 V F.S.IOUT = Actual full scale measured output B. R= 37.5 , IREF = - 8.88 mA C. ZI = 37.5 + 30 pF, IREF = - 8.88 mA D. This parameter is the allowed Pixel Clock frequency variation. It does not permit the Pixel Clock period to vary outside the minimum values for Pixel Clock (tCHCH) period. E. The color palette's pixel address is required to be a valid logic level with the appropriate setup and hold times at each rising edge of PCLK (this requirement includes the blanking period). F. The output delay is measured from the 50% point of the rising edge of CLOCK to the valid analog output. A valid analog output is defined when the analog signal is halfway between its successive values.
Input rise and fall times (10% to 90%) ............................ 3 ns Digital input timing reference level ............................... 1.5 V Digital output timing reference level .............0.8 V and 2.4 V
Capacitance
C1 Digital input............................................................... 7 pF C0 Digital output............................................................. 7 pF C0A Analog output ........................................................ 10 pF
1.4V CLK 200 25 pF
5342_03
Clock Load
G. This applies to different analog outputs on the same device. H. Measured at 200 mV from steady state output voltage. I. This parameter allows synchronization between operations on the microprocessor interface and the pixel stream being processed by the color palette. The following specifications apply for VDD = +5V 0.5V, GND=0. Operating Temperature = 0C to 70C.
General Operation
The ICS5342 GENDAC is intended for use as the analog output stage of raster scan video systems. It contains a highspeed Random Access Memory of 256 x 18-bit words, three 6/8-bit high-speed DACs, a microprocessor/graphic controller interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators. An externally generated BLANK* signal can be applied to pin 7 of the ICS5342. This signal acts on all three of the analog outputs. The BLANK* signal is delayed internally so that it appears with the correct relationship to the pixel bit stream at the analog outputs. A pixel word mask is included to allow the incoming pixel address to be masked. This permits rapid changes to the effec-
J.
K. Except for SENSE pin.
AC Test Conditions
Input pulse levels...................................................VDD to 3V
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ICS5342 GENDAC
tive contents of the color palette RAM to facilitate such operations as animation and flashing objects. Operations on the contents of the mask register can also be totally asynchronous to the pixel stream. The ICS5342 also includes dual PLL frequency generators providing a video clock (CLK0) and a memory clock (CLK1), both generated from a single 14.318 MHz crystal. There are eight selectable CLK0 frequencies. All eight are programmable. There are two selectable and programmable CLK1 frequencies (fA, fB). Default values (Shown in tables: "Video Clock Default Frequency Registers," and "Memory Clock Default Frequency Registers") are loaded into the appropriate registers on power up.
DAC Outputs
The outputs of the DACs are designed to be capable of producing 0.7 V peak white amplitude with an IREF of 8.88 mA when driving a doubly-terminated 75 load. This corresponds to an effective DAC output load (REFFECTIVE) of 37.5 . The formula for calculating IREF with various peak white voltage/output loading combinations is given below:
V PEAKWHITE I REF = -------------------------------------------2.1 x R EFFECTIVE
Note that for all values of IREF and output loading:
V BLACKLEVEL = 0
Video Path
The GENDAC supports nine different video modes and is determined by bits 4-7 of the command register. The default mode is the 8-bit Pseudo Color mode. The other modes are the bypass 15-bit, 16-bit and 24 bit True Color modes in 8-bit and 16-bit interface, and the 16-bit Pseudo Color (2:1) mode with 2X Clock. The 24-bit True Color has sparse and packed modes.
The reference current IREF is determined by the reference voltage VREF and the value of the resistor connected to RSET pin. VREF can be the internal band gap reference voltage or can be overridden by an external voltage. In both cases:
I REF = V REF R SET
VREF
DAC IREF
IREF
Pseudo Color
8-bit Interface In this mode, Pixel Address, P7-P0 and BLANK* inputs are sampled on the rising edge of the clock (PCLK) and any change appears at the analog outputs after three succeeding rising edges of the PCLK. The DAC output depends on the data in the color palette RAM. 16-bit Interface In this mode, Pixel Address, P15-P0 and BLANK* inputs are sampled on the rising edge of the clock (PCLK) and any change appears at the analog outputs after three succeeding rising edges of the 2 x ICLK. ICLK frequency is twice the PCLK input frequency. The DAC output depends on the data in the color palette RAM.
(INT)
36 38 39
VREF
33
34
(EXT)
RSET
REFF
5342_04
DAC Setup The BLANK* input to the GENDAC acts on all three of the DAC outputs. When the BLANK* input is low, the DACs are powered down. The connection between the DAC outputs of the ICS5342 and the RGB inputs of the monitor should be regarded as a transmission line. Impedance changes along the transmission line will result in the reflection of part of the video signal back along the line. These reflections may result in a degradation of the picture displayed by the monitor. RF techniques should be observed to ensure good fidelity. The PCB trace connecting the GENDAC to the off-board connector should be sized to form a transmission line of the correct impedance. Correctly matched RF connectors should be used for connection from the PCB to the monitor coaxial cable and from that cable to the monitor. There are two recommended methods of DAC termination: double termination and buffered signal. Each is described below with its relative merits.
Bypass Mode
The GENDAC supports seven different bypass modes: three for byte transfers and four for word transfers. In these modes, the address pins P0-P15 represent Color Data that is applied directly to the DAC. The internal look-up table RAM is ignored. During byte transfers, the P8-P15 inputs are"don't care." Data is always latched on the rising edge of PCLK. Byte or word framing is internally synchronized with the rising edge of BLANK*.
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ICS5342 GENDAC
Double Termination (Figure 1) For this termination scheme, a load resistor is placed at both the DAC output and the monitor input. The resistor values should be equal to the characteristic impedance of the line. Double termination of the DAC output allows both ends of the transmission line between the DAC outputs and the monitor inputs to be correctly matched.The result should be an ideal reflection-free system. This arrangement is relatively tolerant of variations in transmission line impedance (e.g. a mismatched connector) since no reflections occur from either end of the line. A doubly terminated DAC output will rise faster than any singly terminated output because the rise time of the DAC outputs is dependent on the RC time constant of the load. comparators is proportional to the VREF (internal or external) and is typically 0.330 for VREF=1.235 Volts. The SENSE* pin will be driven low when any analog video output is above 0.385 mV. SENSE* output will be high when all analog outputs are below 275 mV. This signal is used to detect the type of (or lack of) monitor connected to the system.
PLL Clock
The ICS5342 has dual PLL frequency generators for generating the video clock (CLK0) and memory clock (CLK1) needed for graphics subsystems. Both of these clocks are generated from a single 14.318 MHz crystal or they can be driven from an external clock source. The chip includes the capacitors for the crystal and all of the components needed for the PLL loop filters, minimizing board component count. There are eight possible video clock, CLK0, frequencies (f0f7) which can be selected by the external pins CS1-CS0. All clocks are software selectable by setting a bit in the PLL control register. Frequencies f0-f7 can be programmed for any frequency by writing appropriate parameter values to the PLL parameter registers. The default frequencies on power up are commonly used video frequencies (see table "Video Clock Default Frequency Registers"). At power up, the frequencies can be selected by pins CS2-CS0. There are two programmable memory clock frequencies (fA, fB). On power up this frequency defaults to the frequency given in the table: "MemoryClock Default Frequency Registers." The memory clock transition between frequencies is smooth and glitch free if the N2 PLL parameter is not changed from its previous setting. Video Clock (CLK0) Default Frequency Register * Comments fn VCLK M & N Code (MHz) f0 25.175 7D 50 VGA0 (VGA Graphics) f1 28.322 55 49 VGA1 (VGA Text) f2 31.500 2A 43 VESA 640 x 480 @72 Hz f3 36.00 77 4A VESA 800 x 600 @56 Hz f4 40.00 79 49 VESA 800 x 600 @60 Hz f5 44.889 6F 47 1024 x 768 @43 Hz Interlaced f6 65.00 74 2B 1024 x 768 @ 60 Hz, 640 x 480 Hi-Color @ 72 Hz f7 75.00 71 29 VESA 1024 x 768 @ 70 Hz, True Color 640 x 480 * With 14.318 MHz input.
ICS5342
MONITOR
RLOAD
RLOAD
Ground
Ground
5342_05
Double Termination If the GENDAC drives large capacitive loads (for instance long cable runs), it may be necessary to buffer the DAC outputs. The buffer will have a relatively high input impedance. The connection between the DAC outputs and the buffer inputs should also be considered as a transmission line. The buffer output will have a relatively low impedance. It should be matched to the transmission line between it and the monitor with a series terminating resistor. The transmission line should be terminated at the monitor.
RS ICS5342 MONITOR
RLOAD
RT
Ground
Ground
5342_06
Buffered Signal
SENSE Output
The GENDAC contains three comparators, one for each of the DAC output R, G and B lines. The reference voltage to the
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ICS5342 GENDAC
Memory Clock (CLK1) Default Frequency Register fn fA fB MCLK (MHz) 45.00 55.00 M&N Code 4F 2B 79 2E Comments Memory and GUI subsystem clock Memory and GUI subsystem clock Writing new color definitions to a set of consecutive locations in the RAM is made easy by this auto-incrementing feature. First, the start address of the set of locations is written to the write mode Pixel Address register, followed by the color definition of that location. Since the address is incremented after each color definition is written, the color definition for the next location can be written immediately. Thus, the color definitions for consecutive locations can be written sequentially to the Color Value register without re-writing to the Pixel Address register each time. Reading from the RAM To read a color definition, a value specifying the location in the palette RAM to be read is written to the read mode Pixel Address register. After this value has been written, the contents of the location specified are copied to the Color Value register, and the Pixel Address register automatically increments. The red, green and blue intensity values can be read by a sequence of three reads from the Color Value register. After the blue value has been read, the location in the RAM currently specified by the Pixel Address register is copied to the Color Value register and the Pixel Address again automatically increments. A set of color values in consecutive locations can be read simply by writing the start address of the set to the read mode Pixel Address register and then sequentially reading the color values for each location in the set. Whenever the Pixel Address register is updated, any unfinished color definition read or write is aborted and a new one may begin. The Pixel Mask Register The pixel address used to access the RAM through the pixel interface is the result of the bitwise AND-ing of the incoming pixel address and of the contents of the Pixel Mask register. This pixel masking process can be used to alter the displayed colors without altering the video memory or the RAM contents. By partitioning the color definitions by one or more bits in the pixel address, such effects as rapid animation, overlays, and flashing objects can be produced. The Pixel Mask register is independent of the Pixel Address and Color Value registers. The Command Register The Command register is used to select the various GENDAC color modes and to set the power down mode. On power up this register defaults to an 8-bit Pseudo Color mode. This register can be accessed by control pins RS2-RS0, or by a special sequence of events for graphics subsystems that do not have the control signal RS2. For graphic systems that do not have RS2, this pin is tied low and an internal flag (HF: Hidden Flag) is set when the pixel mask register is read four times
Microprocessor Interface
Below are listed the six microprocessor interface registers within the ICS5342, and the register addresses through which they can be accessed. Microprocessor Interface Registers RS2 0 0 0 0 1 1 1 1 0/HF RS1 0 1 0 1 0 0 1 1 1 RS0 0 1 1 0 0 1 0 1 0 Register Name Pixel Address (write mode) Pixel Address (read mode) Color Value Pixel Mask PLL Address (write mode) PLL Parameter Command PLL Address (read mode) Command Register accessed by (hidden) flag after special sequence of events.
Asynchronous Access to Microprocessor Interface Accesses to all registers may occur without reference to the high speed timing of the pixel bit stream being processed by the GENDAC. Data transfers between the color palette RAM and the Color Value register, as well as modifications to the Pixel Mask register, are synchronized to the Pixel Clock by internal logic. This is done in the period between microprocessor interface accesses. Thus, various minimum periods are specified between microprocessor interface accesses to allow the appropriate transfers or modifications to take place. Access to PLL address, PLL parameter and to the command register are asynchronous to the pixel clock. The contents of the palette RAM can be accessed via the Color Value register and the Pixel Address registers. Writing to the color palette RAM To set a new color definition, a value specifying a location in the color palette RAM is first written to the Write mode Pixel Address register. The values for the red, green and blue intensities are then written in succession to the Color Value register. After the blue data is written to the Color Value register, the new color definition is transferred to the RAM, and the Pixel Address register is automatically incremented.
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ICS5342 GENDAC
consecutively. Once the flag is set, the following Read or Write to the pixel mask register is directed to the command register. The flag is reset for read or write to any register other than the Pixel Mask register. The sequence has to be repeated for any subsequent access to the command register. The PLL Parameter Register The CLK0 and CLK1 of the ICS5342 can be programmed for different frequencies by writing different values to the PLL parameter register bank. There are eight registers in the parameter register; seven are two bytes long and one (0E) is one byte long. Writing to the PLL parameter register To write the PLL parameter data, the corresponding address location is first written to the PLL address register. For software compatibility with other chips, two address registers are defined: the write mode PLL address register and the read mode PLL address register. These are actually a single Read/ Write register in the ICS5342. The next PLL parameter write will be directed to the first byte of the address location specified by the PLL address register. The next write to the parameter register will automatically be to the second byte of this register. At the end of the second write the address is automatically incremented. For the one byte "0E" register the address location is incremented after the first byte write. If this frequency is selected while programming, the output frequency will change at the end of the second write. Reading the PLL parameter register To read one of the registers of the PLL parameter register the address value corresponding to the location is first written to the PLL address register. The next PLL parameter read will be directed to the first byte of the address location pointed by this index register. A next read of the parameter register will automatically be the second byte of this register. At the end of the second read, the address location is automatically incremented. The address register (0E) is incremented after the first byte read.
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ICS5342 GENDAC
Functional Description
This section describes the register address and bit definition for the RAMDAC and the Frequency Synthesizer sections. Bit 7-4 Color Mode Select - These three bits select the Color Mode of RAMDAC operation as shown in the following table "Color Mode Select" (default is 0 at power up). (Reserved) Set to `0' for future compatibility. Test Mode - When bit 1 is set checksum accumulation is enabled. If bit 0 is also set the oscillator and synthesizers are turned off for minimum noise. Power Down Mode of RAMDAC - When this bit is set to 0 (default is 0), the device operates normally. If this bit is set to 1, the power and clock to the Color Palette RAM and DACs are turned off. The data in the Color Palette RAM are still preserved. The CPU can access without loss of data by internal automatic clock start/stop control. The DAC outputs become the same as BLANK* (sync) level output during power down mode. This bit does not affect the PLL clock synthesizer function unless test mode is enabled.
Color Palette
Command Register (RS0-RS2 = 011) (RS0-RS1 = 01 with hidden flag) By setting bits 4 and 7-5 in the command register the ICS5342 can be programmed for different color modes and the DACs can be turned off for low power operation. Command Registers 7 2 6 1 5 0 4 3 3 2 Reserved = 0 1 Test mode 0 Snooze
Bit 3-2 Bit 1
Bit 0
Color Mode Select
8-BIT INTERFACE Mode Number 0 1 3 2 1 1 2 3 CM3 (CR4) 0 0 0 0 0 0 0 0 CM2 (CR7) 0 0 0 0 1 1 1 1 CM1 (CR6) 0 0 1 1 0 0 1 1 CM0 (CR5) 0 1 0 1 0 1 0 1 Color Mode 8-bit Pseudo Color With Palette (default) 15-bit Direct Color With Bypass (Hi-Color) 24-Bit True Color With Bypass (True Color) 16-bit Direct Color With Bypass (XGA) 15-bit Direct Color With Bypass (hi-color) 15-bit Direct Color With Bypass (Hi-Color) 15-bit Direct Color With Bypass (Hi-Color) 24-bit True Color With Bypass (True Color) Clock Cycles/ Pixel Bits 1 2 3 2 2 2 2 3
16-BIT INTERFACE Mode Number 4 5 6 7 8 CM3 (CR4) 1 1 1 1 1 1 1 1 CM2 (CR7) 0 0 0 0 1 1 1 1 CM1 (CR6) 0 0 1 1 0 0 1 1 CM0 (CR5) 0 1 0 1 0 1 0 1 Color Mode Multiplexed 16-bit Pseudo Color With Palette 15-bit Direct Color With Bypass (Hi-Color) 16-bit Direct Color With Bypass (XGA 24-bit True Color With Bypass (True Color) 24-bit Packed True Color With Bypass (true-color) Reserved Reserved Reserved Clock Cycles/ Pixel Bits 1/2 1 1 2 3/2
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ICS5342 GENDAC
Color Modes
The nine selectable color modes are described here. Four are eight-bit and five are 16-bit wide pixel input. Color Modes 0-3 are 8-bit interfaces with bits P0-P7; P8-P15 are "don't care" bits. Mode 0: 8-bit Pseudo Color (one clock per pixel). This mode is the 8-bit per pixel Pseudo Color mode. In this mode, inputs P0-P7 are the pixel address for the color palette RAM and are latched on the rising edge of every PCLK. This is the default mode on power up and it is selected by setting bits CR7-CR4 to 0000. 8-bit Pseudo Color - Mode 0 PIXEL BYTE PPPPPPPP 76543210 76543210 LUT ADDRESS Mode 1: (15-bit per color bypass Hi-Color mode). This mode is the 15-bit per pixel bypass mode. In this mode, inputs P0-P7 are the color DATA and are input directly to the DAC, bypassing the color palette. The two bytes of data are latched in two successive PCLK rising edges. ICS5342 supports only the two clock mode and does not support the mode where the data are latched on the rising and the falling edges. For compatibility, the 15/16 one clock modes are selected as two clock modes in this chip. The low-byte, high byte synchronization is internally done by the rising edge of BLANK*. Each color is 5-bit wide and is packed into two bytes as shown below. This mode can be selected by setting bits CR7-CR4 to 0010, 1000 or 1010. 15-Bit Color - Mode 1 SECOND BYTE FIRST BYTE PPPPPPPPPPPPPPPP 7654321076543210 X7 6 5 4 3 7 6 5 4 3 7 6 5 4 3 X RED GREEN BLUE 3LSB = set to zero Mode 2: (16-bit per pixel bypass XGA mode). This mode is the 16-bit per pixel bypass mode and the P0-P7 inputs to go to the DAC directly, bypassing the color palette. The 2 bytes data is latched on two successive rising edges and the lowbyte, high-byte synchronization is internally done by the rising edge of BLANK*. In this mode, blue and red colors are 5 bits wide and green is 6 bits wide. The 2 bytes of data are packed as shown below. This mode can be selected by setting bits CR7-CR4 to 0110 or 1100. 16-Bit Color - Mode 2 SECOND BYTE FIRST BYTE PPPPPPPPPPPPPPPP 7654321076543210 7654376543276543 RED GREEN BLUE 2LSB = set to zero (green) 3LSB = set to zero (blue, red) Mode 3: (24-bit per pixel True Color Mode). This mode is the 24-bit per pixel bypass mode. The three bytes of data are latched on three successive PCLK edges and the first byte is synchronized by the rising edge of BLANK*. In this mode, each of the colors are 8-bit wide and the DAC is an 8-bit wide DAC. The first byte is blue followed by green and red. This mode can be selected by setting bits CR7-CR4 to 0100 or 1110. The DAC outputs changes every three cycles and the pipeline delay from the first byte to output is five cycles. 24-bit Color - Mode 3 THIRD BYTE SECOND BYTE PPPPPPPPPPPPPPPP 7654321076543210 7654321076543210 RED GREEN FIRST BYTE PPPPPPPP 76543210 76543210 BLUE
16 bit Color Modes
Modes 4 - 8 use the 16-bit pixel interface. Mode 4: (8-bit Pseudo Color two pixels per clock) In this mode, inputs P0-P15 are latched on the rising edge of every PCLK. P0-7 and P8-P15 are used for successive addresses for the palette RAM using an internal clock (ICLK) that runs at twice the PCLK frequency. The DAC outputs change twice for every PCLK and the pipeline delay from the first word to output is one and one half cycles. This mode can be selected by setting bits CR7-CR4 to 0001. Multiplexed 8-bit Pseudo Color Word - Mode 4 PIXEL WORD PPPPPPPPPPPPPPPP 1111119876543210 543210 7654321076543210 2nd PIXEL 1st PIXEL ADDRESS ADDRESS Mode 5: (16-bit pixel interface, 15-bit per color bypass HiColor Mode) In this mode inputs P0-P15 are the color data and are input directly to the DAC, bypassing the color palette. The data is latched by the rising edge of PCLK and is pipe-
15
ICS5342 GENDAC
lined to the DAC. The pipeline delay from input to DAC output is three PCLK cycles. Each color is 5-bit wide as shown below. This mode is selected by setting bits CR7-CR4 to 0011. 15-Bit Color Word - Mode 5 PIXEL WORD PPPPPPPPPPPPPPPP 1111119876543210 543210 X7 6 5 5 4 7 6 5 4 3 7 6 5 4 3 X RED GREEN BLUE 3LSB = set to zero Mode 6: (16-bit pixel interface, 16-bit per color bypass XGA mode) In this mode input P0-P15 are the color data and are input directly to the DAC bypassing the color palette. The data is latched by the rising edge of PCLK and is pipelined to the DAC. The pipeline delay, from input to DAC output, is three PCLK cycles. In this mode Blue and Red colors are 5 bits wide, and Green is 6 bits wide. This mode is selected by setting bits CR7-CR4 to 0101. 16-Bit Color Word - Mode 6 PIXEL WORD PPPPPPPPPPPPPPPP 1111119876543210 543210 7654376543276543 RED GREEN BLUE 2LSB = set to zero (GREEN) 3LSB = set to zero (BLUE, RED) Mode 7: (16-bit pixel interface, 24-bit per color bypass TRUE color mode) In this mode inputs P0-P15 are the color data and are input directly to the DAC bypassing the color palette. Two words are latched on two successive rising edge of PCLK to form the 24-bit DAC input. The first word and the lower byte of the second word form the 24-bit pixel input to the DAC. The higher byte of the second word is ignored. The low and high word synchronization is internally done by the rising edge of BLANK*. The pipeline delay from latching of the first word to DAC output is 4 cycles and each pixel is two pixel clocks wide. In this mode, each of the colors are 8-bits wide and the DAC is 8-bit wide DAC. The first byte is Blue followed by Green and Red. This mode is selected by setting bits CR7-CR4 to 0111. 24-Bit Direct Color Word - Mode 7 FIRST WORD PPPPPPPPPPPPPPPP 1111119876543210 543210 7654321076543210 GREEN BLUE SECOND WORD PPPPPPPPPPPPPPPP 1111119876543210 543210 XXXXXXXX7 6 5 4 3 2 1 0 IGNORED RED Mode 8: (16-bit pixel interface packed 24-bit per color bypass TRUE color mode) In this mode inputs P0-P15 are the color data and are input directly to the DAC bypassing the color palette. Three words are latched on three successive rising edges of PCLK to form two successive 24-bit DAC inputs. The 16bit first word and the lower byte of the second word from the first 24-bit pixel input and the second byte of the second word with the 16 bits of the third word from the second 24-bit pixel input. This cycle repeats every three cycles. The three-word synchronization is internally done by the rising edge of BLANK*. The pipeline delay from latching of first word to DAC output is 3 1/2 cycles and each of the colors are 8-bits wide and DAC is 8-bit wide DAC. The first byte is Blue followed by Green and Red. This mode is selected by setting bits CR7-CR4 to 1001. Packed 24-bit Word - Mode 8 1st DAC Cycle SECOND WORD FIRST WORD PPPPPPPPPPPPPPPPPPPPPPPP 765432101111119876543210 765432105432109876543210 RED GREEN BLUE 2nd DAC Cycle THIRD WORD PPPPPPPPPPPPPPPP 1111119876543210 543210 7654321076543210 RED GREEN
SECOND WORD PPPPPPPP 11111198 543210 76543210 BLUE
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ICS5342 GENDAC
Frequency Generators
The ICS5342 clock synthesizer can be reprogrammed through the microprocessor interface for any set of frequencies. This is done by writing appropriate values to the PLL Parameter Register Bank (See following table: "PLL Parameter Registers").
PLL Control Register
Bits in this register determine internal or external CLK0 select. PLL Control Register 7 6 5 4 3 2 1 0 (RV)= (RV)= ENBL CLK1 (RV)= Internal Select 0 0 INCS SEL 0 X X X Bit 7,6, 3 Reserved, set to `0' for future compatibility. Bit 5 Enable Internal Clock Select (INCS) for CLK0. When this bit is set to 1, the CLK0 output frequency is selected by bits 2-0 in this register. External pins CS0-CS2 are ignored. Bit 4 Clk1 Select when this bit is set to 0, fA is selected. When it is set to 1, fB is selected. The default is 0 for fA selected at power up. Bit 2 - 0 Internal Clock Select for CLK0 (INCS). These three bits select the CLK0 output frequency if bit 5 of this register is on. They are interpreted as an octal number, n, that selects fn. Default selects f0.
PLL Address Registers
The address of the parameter register is written to the PLL address registers before accessing the parameter register. This register is accessed by register select pins RS2-RS0 = 100 or 111. PLL Address Register 76543210 PLL Register Adr. 76543210
PLL Parameters Registers
There are sixteen registers in the PLL parameter register (table 5). Registers 00 to 07 are for the CLK0 selectable frequency list, Register 0A and 0B for CLK1 programmable frequency and register 0E is the PLL control register. PLL Parameter Registers Index 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F R/W R/W R/W R/W R/W R/W R/W R/W R/W R/R/W R/W R/W R/R/R/W R/Register CLK0 f0 PLL Parameters CLK0 f1 PLL Parameters CLK0 f2 PLL Parameters CLK0 f3 PLL Parameters CLK0 f4 PLL Parameters CLK0 f5 PLL Parameters CLK0 f6 PLL Parameters CLK0 f7 PLL Parameters (Reserved) = 0 CLK1 fA PLL CLK1 fB PLL (Reserved) = 0 (Reserved) = 0 (Reserved) = 0 PLL Control Register (Reserved) = 0 (2 bytes) (2 bytes) (2 bytes) (2 bytes) (2 bytes) (2 bytes) (2 bytes) (2 bytes) (2 bytes (2 bytes) (2 bytes) (2 bytes (2 bytes) (2 bytes) (1-byte) (2 bytes)
PLL Data Registers
The CLK0 and CLK1 output frequency is determined by the parameter values in this register. These are two-byte registers; the first byte is the M-byte and the second the N-byte. M-Byte PLL Parameter Input The M-byte has a 7-bit value (1-127) which is the feedback divider of the PLL. M-Byte 7 6 Reserved =0 X 5 X 4 3 2 M-Divider Value X X X 1 X 0 X
N-Byte PLL Parameter Input The N-byte contains two parameter values. N1 sets a 5-bit value (1-31) for the input pre scalar and N2 is a 2-bit code for selecting 1, 2, 4, or 8 post divide clock output. N-Byte PLL Parameter Input 7 6 5 4 3 2 1 Reserved N2 - Code N1-Divider Value =0 X X X X X X
0 X
17
ICS5342 GENDAC
N2 Post Divide Code If mode 4 is set in the command register, CR7-CR4 bits equal 0001, and the N2 code must be 10. N2 Post Divide Code N2 Code 00 01 10 11 1 2 4 8 Divider
Additional Information on Programming the Frequency Generator section of the GENDAC
When programming the GENDAC PLL parameter registers, there are many possible combinations of parameters which will give the correct output frequency. Some combinations are better than others, however. Here is a method to determine how the registers need to be set: The key guidelines come from the operation of the phase locked loop, which has the following restrictions: 1.
2 MHz < f REF < 25 MHz This refers to the input refer-
The block diagram of the PLL clock synthesizer is shown in figure 3. Based on the M and N values, the output frequency of the clocks is given by the following equation:
( M + 2 )F REF F OUT = -------------------------------2 N 2 ( N1 + 2 )
ence frequency. Most users simply connect a 14.318 MHz crystal to the crystal inputs, so this is not a problem. 2.
f REF 600KHz ---------------- 8MHz This is the frequency input to N1 + 2
M and N values should be programmed such that the frequency of the VC0 is within the optimum range for duty cycle, jitter and glitch free transition. Optimum duty cycle is achieved by programming N2 for values greater than unity. See the next section for a programming example.
the phase detector. 3.
M+2 60MHz ---------------- f REF 270 MHz N1 + 2
This is the VCO
Programming Example
Suppose an output frequency of 25.175 MHz is desired. The reference crystal is 14.318 MHz. The VCO should be targeted to run in the 60 to 270 MHz range, so choosing a post divide of 4 gives a VCO frequency of:
4 x 25.175 = 101.021 MHz
frequency. In general, the VCO should run as fast as possible, because it has lower jitter at higher frequencies. Also, running the VCO at multiples of the desired frequency allows the use of output divides, which tends to improve the duty cycle. 4.
f CLK 0 and f CLK 1 35 MHz
This is the output fre-
quency. These rules lead to the following procedure for determining the PLL parameters, assuming rules 1 and 4 are satisfied. A. Determine the value of N2 (either 1, 2, 4 or 8) by selecting the highest value of N2, which satisfies the condition N2* fCLK < 270 Mhz.
From the table in the previous section, we find N2 = 2 Substituting FREF = 14.318 and 2N2 = 4 into the clock frequency equation in the previous section:
25.175 M+2 --------------- 4 = ---------------14.318 N1 + 2
B. Calculate:
2 N 2 f OUT M+2 ---------------- = ---------------------N1 + 2 f REF
By trial and error: M + 2 = 127 M = 125 N1 + 2 = 18 N1 = 16 so the registers are: M = 125d = 1 1 1 1 1 0 1 b N = 0 & N2 code & N1 = 0 & 1 0 & 1 0 0 0 0 N=01010000b
C. Now (M+2) and (N1+2) must be found by trial and error. With a 14.318 MHz reference frequency, there will generally be a small output frequency error due to the resolution limit of (M+2) and (N1+2). For a given frequency tolerance, several different (M+2) and (N1+2) combinations can usually be found. Usually, a few minutes trying
18
ICS5342 GENDAC
out numbers with a calculator will produce a workable combination. Multiplying possible values of (N1+2) by the desired ratio will indicate approximately the value of M. This method is shown in the example below. A program could be written to try all possible combinations of (M+2) and (N1+2) (3937 possible combinations). Discard those outside the error band, and select from those remaining by giving preference to ratios which use lower values of (M+2). Lower values of (M+2) and (N1+2) provide better noise rejection in the phase locked loop. Example: Suppose you have a 14.318 MHz reference crystal and want an output frequency of 66 MHz. You want to limit the VCO frequency to 240 Mhz and have an error of no greater than 0.5%. What are the values of the PLL data registers? A. 66*8 = 528 > 250 -- VCO speed too high 66*4 = 264 > 250 -- VCO speed too high 66*2 = 132 < 250 -- VCO speed OK, N2 = 2, N2 code = 01 from the Post Divide Code table in the PLL Data Registers section. B. 132/14.31818 = 9.219 This is the desired frequency multiplication ratio. C. Setting (N1+2) = 3,4, ...12, 13 and performing some simple calculations yields the following table: (Note that N1 cannot be 0). The ratio 83/9 is closest. Thus: (N2+2) = 9 N2=7 (M+2) = 83 M = 81 The M-byte PLL parameter word is simply 81 in binary, plus bit 7 (which must be set to 0), or 01010001. The N-byte PLL parameter word is N2 code (01) concatenated with 5 bits of N2 in binary (00111), or 00100111. Once again, bit 7 must be zero. The combination with the least frequency error was chosen, but several other combinations are within the 0.5% tolerance. Because the lowest value of (M+2) offers the best damping, the 37/4 combination will have the best power supply rejection. This results in lower jitter due to external noise.
Example Calculation of PLL Data Register Values (N1 + 2) 3 4 5 6 7 8 9 10 11 12 13 (N1 + 2) *9.219 27.657 36.876 46.095 55.314 64.533 73.752 82.971 92.19 101.409 110.628 119.847 rounded (=M + 2) 28 37 46 55 65 74 83 92 101 111 120 Actual Ratio 9.33 9.25 9.20 9.17 9.29 9.25 9.22 9.20 9.18 9.25 9.23 Percent Error -1.23 -0.34 0.21 0.57 -0.72 -0.34 -0.03 0.21 0.40 -0.34 -0.13
19
ICS5342 GENDAC
Fref
1/(N1+2)
PHASE DETECT
CHARGE PUMP
LOOP FILTER
VCO
N2 COUNTER
1/(M1+2)
5342_07
PLL Clock Synthesizer Block Diagram Video Clock Selection Table
External Select CS2 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 CS0 0 1 0 1 0 1 0 1 (Internal Select PLL Control Register) BIT 2 0 0 0 0 1 1 1 1 BIT 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 1 0 1 0 1 CLK 0 Frequency f0 f1 f2 f3 f4 f5 f6 f7
20
ICS5342 GENDAC
PCLK P0-P7
A B C D E F G H I J K
BLANK
B C F BLANK G
RED
A
B
F C BLANK G
GREEN
A
A
C B BLANK F
G
5342_8
BLUE
System Timing - Pseudo Color, Mode 0
tCHCL
tCHCH
tCLCH
PLCK
tPVCH tCLPX
E
tBVCH
F
G
tCHBX
H
I
J
K
BLANK
tCHAV
RED
A
B
tCHAV
C BLANK F
G
B A A BLUE B C
tCHAV
F BLANK
G
C BLANK
F
G
5342_09
Detailed Timing Specifications - Pseudo Color, Mode 0
21
ICS5342 GENDAC
PCLK
1
2
3
4
5
6
7
BLANK
P0-P7
LOW BYTE A
HIGH BYTE A
LOW BYTE B
HIGH BYTE B
DAC-RD
A A
B
DAC-GR
B B
5342_10
DAC-BL
A
System Timing Bypass- 15(5/6/5) Modes 1,2
0ns PCLK
25ns 1 2 A
50ns 3 4
75ns 5 B 6 7
100ns 8 C 9
125ns
150ns
BLANK
P0-P7
BL
GR
RD
BL
GR
RD
DAC-BL DAC-GR A C
5342_11
DAC-RD
B
System Timing Bypass True Color 24 (8,8,8) Mode 3
22
ICS5342 GENDAC
PCLK ICLK
A C E G J L N 1 1 1 1 1 1 1
P0-P7 P8-P15 BLANK
B
D
F
H
K
M
P
C
RED GREEN BLUE
A
B B
D
J BLANK
K
L
A
C
D D
BLANK
J
L L
A B
C
J BLANK K
5342_12
System Timing - 8-bit Pseudo Color, Mode 4
PCLK
1 2 3 4 5 6 7
P0-P7
A
B
C
D
E
F
G
H
BLANK
RED
A
B BLANK
A
B BLANK
GREEN
A
BLUE
B BLANK
5342_13
System Timing - 16-bit Color, Mode 5(5,5,5) and 6((5,6,5)
23
ICS5342 GENDAC
PCLK
1 2 3 4 5 6 7
P0-P7
Ab Ag
Ar --
Bb Bg
Br --
Cb Cg
Cr --
Db Dg
Dr --
BLANK
RED
A
BLANK
A
GREEN
BLANK
BLUE
A
BLANK
5342_14
System Timing - 16-bit Direct True Color, Mode 7
PCLK P0-P7
AL AM
1
2
3
4
5
6
7
AU BL
BM BU
CL CM
CU DL
DM DU
EL EM
EU FL
FM FU
GL GM
BLANK
B
RED
A
BLANK
BLANK
GREEN
A
B
BLANK
BLANK
A
BLUE
B
BLANK
BLANK
5342_15
System Timing - 24-bit Packed Color, Mode 8
24
ICS5342 GENDAC
tWLWH WR* tSVWL RS0-RS1 tDVWH D0-D7 tWHDX tWLSX
Basic Write Cycle Timing
tRLRH RD* tSVRL RS0-RS1 tRLQV D0-D7 tRLQX tRHQZ tRHQX tRLSX
Basic Read Cycle Timing
5342_16
tWHWL1 WR* RD* RS0 RS1
tWHRL1
Write to Pixel Mask Register Followed by Write
WR* tRHRL1 RD*
Write to Pixel Mask Register Followed by Read
tRHWL1
Read from Pixel or Pixel Address Register (Read or Write) followed by Read
Read from Pixel or Pixel Address Register (Read or Write) followed by Write
5342_17
Read-Write Timing
25
ICS5342 GENDAC
WR* tWHRL1
RD* RS0
RS1
RS2
D0-D7
ADDRESS
ADDRESS+1
5342_18
W it d Back k Pi l Add R i t (R d M d ) Write and ReadR d BPixel Address Register (Read Mode)
WR*
tWHRL3
RD* RS0
RS1
RS2
D0-D7
ADDRESS
ADDRESS
5342_19
Write and Read Back Pixel Address Register (Write Mode)
26
ICS5342 GENDAC
WR*
tWHRL3
tRHRL1
tRHRL1
tRHRL2
RD* RS0
RS1
RS2
D0-D7
ADDRESS
RED
GREEN
BLUE
ADDRESS+2
5342_20
Read Color Value then Pixel Address Register (Read Mode)
tWHWL1 WR* tWHRL2 RD* tWHWL1 tWHWL1
RS0
RS1
RS2
D0-D7
ADDRESS
RED
GREEN
BLUE
5342_21
Color Value Write Followed by any Read
27
ICS5342 GENDAC
tWHWL1 tWHWL1 tWHWL1 tWHWL2
WR*
RD* RS0
RS1
RS2
D0-D7
ADDRESS
RED
GREEN
BLUE
5342_22
Color Value Write Followed by any Write
WR*
tWHRL3
tRHRL1
tRHRL1
tRHRL2
RD* RS0
RS1
RS2
D0-D7
ADDRESS
RED
GREEN
BLUE
5342_23
Color Value Read Followed by any Read
28
ICS5342 GENDAC
WR*
tWHRL3
tRHRL1
tRHRL1
tRHWL2
RD* RS0
RS1
RS2
D0-D7
ADDRESS
RED
GREEN
BLUE
5342_24
Color Value Read Followed by any Write
WR*
tWHRL3
RD* RS0
RS1
RS2
D0-D7
ADDRESS
ADDRESS
5342_25
Write and Read back PLL Address Register (Write Mode)
29
ICS5342 GENDAC
WR*
tWHRL3
RD* RS0
RS1
RS2
D0-D7
ADDRESS
ADDRESS+1
5342_26
Write and Read back PLL Address Register (Read Mode)
WR*
tWHRL3
tRHRL1
tRHRL1
tRHRL2
RD* RS0
RS1
RS2
D0-D7
PLL ADDRESS
PLL LOW
PLL HIGH
ADR+1
5342_27
ReadR d T B PLLPLL R i t then PLL AddressR i t Two bytes t Register th PLL Add Register
30
ICS5342 GENDAC
WR*
tWHRL3
tRHRL1
tRHRL1
tRHRL2
RD* RS0
RS1
RS2
D0-D7
ADDRESS
PLL
ADR+1
5342_28
Read One Byte PLL Register then PLL Address Register
RED GREEN BLUE 0.335V tS0D SENSE
5342_29
Monitor SENSE Signal
31
ICS5342 GENDAC
Recommended Layout
LOCATE NEAR CONTROLLER
R4
R4
LOCATE NEAR CONTROLLER
C2
R2
C2
R1
CGND
CVDD 9
CLK1
27 CVDD 28 29 30 31 32 33 34 35 36 AGND 37 RED 38 GRN 39
DGND
40 BLUE 41 AVDD 42 RSET 43 DVDD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CLK0
R2
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
CGND 60
GENDAC II ICS5342
59 58 57 56 55 54 53 52 51 XVDD 50 XOUT 49 XIN 48 XGND 47 VREF 46 45 44
PCLK
R5
C2
VAA
Y1
DGND C2
C1
C2
C2
FB1
C3 -
C1
VAA
VAA
R3
5342_30
Board Layout and Analog Signal Considerations
The high performance of the GENDAC is dependent on careful PC board layout. The use of a four layer board (internal power and ground planes, signals on the two surface layers) is recommended. The ground plane layer should be closest to the component side of the board. The layout following this section shows a suggested configuration.
-
+
VIA to power plane VIA to ground plane C1 0.047 F chip capacitor C2 0.1 F chip capacitor C3 10 F tantalum capacitor FB1 ferrite bead, Fair-Rite 2743019447 R1 33 ohm R2 100 ohm R3 141 ohm, 1% R4 220 ohm R5 560 ohm Y1 parallel resonant crystal cut for CL = 12 pF
Power Supply
As a high speed CMOS device, the GENDAC may draw large transient currents from the power supply. It is necessary to adopt high-frequency board-layout and power-distribution techniques to assure proper operation of the GENDAC. This will also minimize radio frequency interference (RFI). DAC to DAC crosstalk can also be attributed to a high impedance power supply.
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ICS5342 GENDAC
Note the power plane is not separated into analog and digital supply regions. The power and ground planes are continuous, not split. Power is supplied to the analog power pins through the ferrite bead, and bypassed at the power entry point by C3, a 10 F tantalum capacitor. Analog power connections should be routed as shown in the diagram. They may be routed on the back side so the analog signals are routed without vias. Power pins 9 and 43 should be connected to digital power. Power pins 27, 41 and 50 are connected to analog power (VAA). Ceramic decoupling capacitors (indicated by C1 and C2) should be placed as close to the GENDAC as possible. The power traces should be routed through the capacitor pads and the ground vias should not be shared. The rule is: one pad, one via. The GENDAC analog ground pins should have multiple vias to the ground plane, if possible. To supply the transient currents required, the impedance in the decoupling path should be kept to a minimum. It is just as important that the connection between the capacitor ground pad and the ground plane be short and direct. It is recommended that the decoupling capacitance between VDD and GND should be a 0.047 F to 0.1 F high frequency capacitor. Chip capacitors have the lowest lead inductance and are highly recommended. 0.047 F chip capacitors are more effective at frequencies above 80 MHz than other values in the range of 0.022 F to 0.1 F. All supply pins must have a ceramic capacitor connected. A tantalum capacitor with a value between 10 F and 22 F is recommended to decouple low frequencies. To further reduce power-supply noise, a ferrite bead may be added in series with the positive supply to form a low pass filter, as shown in the layout example. Power and ground traces to the GENDAC should be 50 mils wide whenever possible. on the GENDAC. The effect this will have is to compromise the low time and duty cycle of the output clocks. The PCB traces between the outputs of the TTL devices driving the GENDAC and the input to the GENDAC behave like low impedance transmission lines. The trace is driven from a low impedance source and terminated with a high impedance. In accordance with transmission line principles, signal transitions will be reflected from the high impedance input to the device. Similarly, signal transitions will be inverted and reflected from the low impedance TTL output. Termination is necessary to reduce or eliminate ringing; particularly the undershoot caused by reflections. Termination may either be series or parallel. Series and parallel termination is the recommended technique to use. This is accomplished by placing a resistor in series with the signal at the output of the clock driver. The resistor matches the output buffer impedance to that of the transmission line. At the far end of the line another resistor is added to terminate the transmission line to VCC. To minimize reflections, some experimentation is necessary to find the proper value to use for the series termination. Generally, a series resistor with a value around 75, and a parallel resistor of 330 will be satisfactory. Since each design will result in a different trace impedance, a resistor of a predetermined value may not properly match the signal path impedance. The proper value of resistance should be found empirically.
Analog Signals
All analog and digital I/O lines are not shown. Analog signals (DAC outputs, VREF, RSET) should only be routed on the top side of the board. DAC output termination resistors should be located as close as possible to the GENDAC for best signal quality. Doing this will also reduce RFI.
Digital Input Information
To minimize differential ground noise between components on the board, the impedance in the ground supply between the GENDAC and the digital devices driving it should be minimized. This or a high impedance ground trace on the controller may cause false signals to the GENDAC. This can appear as glitches on edge sensitive inputs such as RD*, WR*, and STRB. Splitting the ground plane exacerbates this problem. The combination of series impedance in the ground supply to the GENDAC and transients in the current drawn by the device, will appear as voltage differences across the GND pins
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ICS5342 GENDAC
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ICS5342 GENDAC
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ICS5342 GENDAC
Package Outline
PIN 1 IDENTIFIER
61
0.045
9
0.045
0.985 - 0.995 (25.02 - 25.27)
0.950 - 0.958 (24.13 - 24.33)
GENDAC II ICS5342
0.890 - 0.930 (22.61 - 23.62)
0.013 - 0.021 (0.33 - 0.53)
27
0.985 - 0.995 (25.02 - 25.27) 0.950 - 0.958 (24.13 - 24.33)
43
0.020 (0.51) 0.102 (2.59) 0.165 - 0.180 (4.20 - 4.57) LEAD PITCH 0.050 TYPICAL DIMENSIONS: INCHES (MILLIMETERS)
5342_31
68 PIN PLCC
Package Detail
36

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